A Case Study in Predictive Three-Dimensional Topography Simulation Based on a Level-Set Algorithm

The aim of this work is to study the etching of trenches in silicon and the generation of voids during the filling of genuinely three-dimensional trench structures with silicon dioxide or nitride. The trenches studied are part of the manufacturing process of power MOSFETs, where void-less filling must be achieved. Another area of applications is capacitance extraction in interconnect structures, where the deliberate inclusion of voids serves the purpose of reducing overall capacitance. Furthermore, these simulations make it possible to analyze the variations on the feature scale depending on the position of the single trench on the wafer and in the reactor.